Is there any way to get 2 physical cores in a travic ci environment?

We are using Travis CI for automated testing of a High Performance Computing library. It typically runs on HPC systems (like a cluster or a Cray) . These type of system have many nodes each with many cores . Our library uses both MPI and threads for parallelism, and our regression tests exercise serial, MPI and MPI+threads mode. Typically we do not use hyperthreads because profiling showed that they hurt performance. Some MPI libraries also abort when they detect that you are running on hyperthreads instead of physical cores, eg OpenMPI. So we only use phyiscal cores for parallelism. When running the regression tests on Travis CI we find 1 Physical core and 1 hyperthread(see output of /proc/cpuinfo below) and because we don’t use hyperthreads our serial, MPI, and MPI+threads essentially all run in serial with one process and 1 thread. As a result we don’t have coverage for the MPI and MPI+threads modes.

Is there any way to get 2 physical cores in a travic ci environment?

for reference here is the output of /proc/cpuinfo from TravisCI linux environment. It shows 1 core with 2 hyperthreads.

processor    : 0
vendor_id    : GenuineIntel
cpu family    : 6
model        : 85
model name    : Intel(R) Xeon(R) CPU
stepping    : 7
microcode    : 0x1
cpu MHz        : 2800.184
cache size    : 33792 KB
physical id    : 0
siblings    : 2
core id        : 0
cpu cores    : 1
apicid        : 0
initial apicid    : 0
fpu        : yes
fpu_exception    : yes
cpuid level    : 13
wp        : yes
flags        : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ss ht syscall nx pdpe1gb rdtscp lm constant_tsc rep_good nopl xtopology nonstop_tsc cpuid tsc_known_freq pni pclmulqdq ssse3 fma cx16 pcid sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand hypervisor lahf_lm abm 3dnowprefetch invpcid_single ssbd ibrs ibpb stibp ibrs_enhanced fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm mpx avx512f avx512dq rdseed adx smap clflushopt clwb avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves arat avx512_vnni md_clear arch_capabilities
bugs        : spectre_v1 spectre_v2 spec_store_bypass mds swapgs taa
bogomips    : 5600.36
clflush size    : 64
cache_alignment    : 64
address sizes    : 46 bits physical, 48 bits virtual
power management:

processor    : 1
vendor_id    : GenuineIntel
cpu family    : 6
model        : 85
model name    : Intel(R) Xeon(R) CPU
stepping    : 7
microcode    : 0x1
cpu MHz        : 2800.184
cache size    : 33792 KB
physical id    : 0
siblings    : 2
core id        : 0
cpu cores    : 1
apicid        : 1
initial apicid    : 1
fpu        : yes
fpu_exception    : yes
cpuid level    : 13
wp        : yes
flags        : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ss ht syscall nx pdpe1gb rdtscp lm constant_tsc rep_good nopl xtopology nonstop_tsc cpuid tsc_known_freq pni pclmulqdq ssse3 fma cx16 pcid sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand hypervisor lahf_lm abm 3dnowprefetch invpcid_single ssbd ibrs ibpb stibp ibrs_enhanced fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm mpx avx512f avx512dq rdseed adx smap clflushopt clwb avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves arat avx512_vnni md_clear arch_capabilities
bugs        : spectre_v1 spectre_v2 spec_store_bypass mds swapgs taa
bogomips    : 5600.36
clflush size    : 64
cache_alignment    : 64
address sizes    : 46 bits physical, 48 bits virtual
power management:
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